This invention pertains to computer control systems and more particularly to those systems utilizing twin computers operating in parallel-synchronous cooperation.
In real time systems such as stored program controlled telecommunication systems it has been common to employ control computers using unified-bus principles. Typically, in such systems the computer which controls the telecommunication devices or units is in turn controlled by a clock generator. Within the computer the operating units are all connected to a common or unified bus. Typical unified-bus computers used in telecommunication systems are the No. 2 ESS Call Processor whose block diagram is shown on page 2634 of The Bell System Technical Journal of October 1969, and the computer disclosed in U.S. Pat. No. 3,631,401 and called a Direct Function Data Processor.
Such computers and particularly that of said patent have an order bus and a data bus in addition to timing circuits. It is because of the bus configuration that such computers can be easily modified, expanded or modernized as new components become available. This flexibility is highly desirable. More particularly, because a unified-bus system comprises a number of parallel wires for transmission in parallel and digital form of data (data bus), addresses and order in parallel (order bus) and to which wires all the computer parts are connected, there is obtained a modular-system principle with the function or operating units of the computer being the modules. The function units are connected to the unified-bus system in a uniform manner by uniform interfaces, for example in the form of buffer registers accessable by encoding. By choosing suitable modules there is obtained the most varying computer constructions, such as minicomputers, microcomputers, calculators or real-time computers to control simple or complicated processes.
The unified-bus modular system is also used when building real-time controlled telecommunication systems. The demands for real-time controlling of telecommunication processes often necessitate to distinguish between fast and slow acting function units, i.e. to introduce different bus systems for different data processing speeds and to provide buffer units with the interface for constituting the connection means between the bus systems. If the central function units which carry out the computers own operations and the buffer units between the central and peripheral units are constructed with very fast reacting logical components such as TTL-(Transistor-Transistor-Logic)-circuits and are connected to a central bus system, the properties of the central bus system constitute a limit which must be observed in the determination of the resulting data processing speed. The data transmission speed available on a bus is namely influenced by the interface-number, i.e., the number of connected function units, and by the physical length of the wires in the bus system. A suitable limitation of the number of central parts consequently results in optimum short processing cycles for data processing instructions transferred via the central bus system and results consequently in a very effective real-time controlling of the telecommunication process.
Since transient phenomena arise in connection with a change of the logical condition (changes in the states of the signals on the wires of the buses) of the bus system phase division of the processing cycles in necessary, and with the purpose to obtain the fastest possible data processing, the frequency of the clock generator (the basic timing of the computer) is chosen so high that the delay in time because of such transient phenomena and such reaction times of the components is just about controlled. For example, clock pulse frequencies of 20 MHz and processing cycles of 200 ns are typical.
These delays inherent in unified-bus systems can cause problems. Nevertheless, because of the modularity advantages of such systems, they are used. However, attention must be paid to the properties of such a bus system when designing processing cycles for the data processing instructions and when connecting the computer to further means, for example to a data transferring channel.
Generally there may be instructions of different types associated with processing cycles consisting of different numbers of timing phases defined by means of timing pulses generated by the clock generator. In a computer provided with the unified-bus, data transfer instructions demand the longest processing cycles because the bus system and two function units are involved, the first one sending data and the other one receiving data. Other instructions which require only one of the function units to carry out a function demand usually shorter processing cycles.
The above-discussed systems however have low reliability in telecommunication systems. A fault in the operation of the computer causes a down-time of the telecommunication process. It is possible that the down-time includes a period during which the computer sends nonsense to the devices before the fault is discovered and the whole system is cut off. The down-time includes further diagnostic time to localize the fault, as well as to repair the computer and to restart the system. There are known many methods for increasing the reliablity of a real-time system. At page 57 of Design Of Real Time Computer Systems, by J. Martin published in 1967 by Prentice-Hall, Englewood Cliffs, N.J., there are shown many examples of configurations using two computers. What in the present application is called "parallel-synchronous co-operation" corresponds on said page 57 to the so-called "twin-configuration". In particular, there are two substantially identical computers A and B. Both computers A and B receive the process data being processed identically. In the present application, the computer which sends process data to the telecommunication equipment is called the executive computer, while the other of the two computers is called reserve computer. The results obtained in processing by the computers are compared. If the results do not agree, the control of the telecommunication equipment is interrupted. A first down-time period exists until it is established which computer is faulty. Then the fault-free computer continues to send process data to the equipments. It is important to localize and repair the fault as soon as possible because during the period for localization and repair the reliability is the same as for a single computer system. After the repairing of the faulty computer, the twin-configuration is renewed, the repaired computer now being the reserve computer. However, the following result comparisons are meaningless as long as the reserve computer is not updated i.e., loaded with the same information being processed by the executive computer. Thus it is known to allow a second down-time period during which all updating is carried out.